Image:Mips32 addi.svg

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Mips32_addi.svg‎ (SVG file, nominally 500 × 180 pixels, file size: 15 KB)

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Summary

Description

This figure demonstrates how one type of MIPS32 instruction word is decoded. The first six bits specify the operation (add immediate). The second and third groups of five bits each specify the number of one of MIPS32's 32 general-purpose registers (GPR). The first group specifies the destination GPR, and the second specifies the source GPR. The last sixteen bits specify the immediate value, that is, the 16-bit signed (two's compliment) integer that is added to the second register and then stored in the first register. The equivalent mnemonic in MIPS32 assembly is also shown. This instruction word would cause a MIPS32 CPU to add 350 to the value stored in $r2 and store the result in $r1. If an arithmetic overflow occurs, $r1 is not modified and an overflow flag is set.
Source

http://en.wikipedia.org/wiki/Image:Mips32_addi.svg
Date

2006-07-02
Author

en:User:Booyabazooka
Permission
( Reusing this image)
I, the copyright holder of this work, have published or hereby publish it under the following license:
GNU head Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation license, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled " GNU Free Documentation license".

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Licensing

GNU head Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts.
Subject to disclaimers.

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File history

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Date/Time Dimensions User Comment
current 12:39, 12 November 2006 500×180 (15 KB) German ({{Information |Description=This figure demonstrates how one type of MIPS32 instruction word is decoded. The first six bits specify the operation (add immediate). The second and third groups of five bits each specify the number of one of MIPS32's 32 genera)
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